library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder is
    port(
    a, b: in std_logic_vector(31 downto 0);
    s: out std_logic_vector(31 downto 0)
    );
end adder;

architecture behav of adder is
begin
    s <= a + b;
end behav;
